1. Field of the Invention
The present invention relates to a driving circuit and data driver of a planar display device.
2. Description of Related Art
As a dot matrix display device, a liquid crystal display device has been used for various types of devices such as a personal computer because it has characteristics of thin, light, and low-power consumption. In particular, an active matrix color liquid crystal display device, which has an advantage in controlling high definition image quality, has been the mainstream of it.
A liquid crystal display module of this type of liquid crystal display device includes: a liquid crystal panel (LCD panel); a control circuit (hereinafter referred to as a controller) formed of a semiconductor integrated circuit device (hereinafter referred to as an IC); a scanning-side driving circuit (hereinafter referred to as a scanning driver) formed of the IC; and a data-side driving circuit (hereinafter referred to as “data driver”). In many cases, more than one data drivers are provided to a device. For example, if a resolution, of the liquid crystal panel is XGA (1024×768 pixels: one pixel is formed of three dots of R (red), G (green) and B (blue)), eight data drivers are arranged, each covering 128 pixels.
Each data driver converts digital data signals for one scanning line, which are supplied from the controller for each scanning line of the Liquid crystal panel (for each horizontal interval), into analog gradation voltages, and then applies the resultant digital data signals to a data line of the liquid crystal panel. As an internal fundamental circuit, each data driver has a shift register, a data register, a data latch circuit, and a driver circuit, while being cascade-connected by input and output of the shift register.
The controller commonly supplies a clock signal, a digital data signal and a latch signal to each data driver. Thus, a start signal is supplied to the first-stage data driver. The start signal supplied to the first-stage data driver is transferred to the cascade-connected second-stage data driver and the subsequent cascade-connected data drivers in a sequential manner, so that the eight shift registers of the eight data drivers can operate as one shift register. In response to the start signal, the shift register of each data driver outputs, to the data register, a shift pulse for fetching display data, which sequentially shift in synchronization with the clock signal. The data register of each data driver sequentially fetches the data signal in synchronization with the shift pulse. The data latch circuit of each data driver fetches the data signal supplied from the data register in synchronization with the latch signal, holds the fetched data signal until the latch signal is supplied for the next time, that is, for one horizontal interval, and outputs the data signal to the driver circuit. The driver circuit performs D/A conversion and amplification of the data signal from the data latch circuit, and then outputs the resultant data signal to the data line of the liquid crystal panel. At this time, the data latch circuit performs a fetching operation at the leading edge of the latch signal. At the same time of the fetching operation of the data latch circuit, the driver circuit disconnects the data output so as not to output, to the data line, the values in a transitional state of D/A converting. After that, the output of the driver circuit is connected to the data line at a trailing edge of the latch signal so as to output new data to the data line.
And now, in the above-mentioned liquid crystal display device, one latch signal supplied from the controller is commonly inputted to the data latch circuit of each data driver. For this reason, the data latch circuits of all the data drivers simultaneously perform a latch operation in synchronization with this latch signal. When the number of pixels increases, since the liquid crystal panel becomes to have higher definition image quality and a larger size, the number of stages of the latch configuring the data latch circuit also increases as an entire liquid crystal display device. When the above-mentioned latch operations are simultaneously performed by the data drivers under such a circumstance, currents relating to the latch operations of all the data drivers simultaneously flow to a power-supply line common in the display device, which results in increasing electro-magnetic interference (hereinafter referred to as “EMI”).
Japanese Patent Application Laid-open publication No. 8-22268 discloses a technology to solve this problem. In this patent document, there is disclosed a liquid crystal driving circuit that fetches image data serially inputted in synchronization with a clock pulse and outputs in parallel a display output signal formed based on the serially-fetched image data according to a display timing signal. In this liquid crystal driving circuit, an output circuit and an output terminal are provided in addition to an input terminal, and multiple liquid crystal driving circuits are cascade-connected. In this liquid crystal display circuit, an internal wiring and an output circuit are used as delay means, so that the output timing of the display signal for, each liquid crystal driving circuit is temporally dispersed. Thus, the above-mentioned problem can be resolved. It is to be noted that in the example of Japanese Patent Application Laid-open publication No. 8-22268, in addition to the display timing signal, the image data and the clock pulse are sequentially transferred to each of the cascade-connected liquid crystal driving circuits through the delay means, instead of not commonly supplied to each of the liquid crystal display circuits. In this way, a relative temporal relationship between the display timing signal and the image data or the clock pulse is maintained, so as not to cause any problem in fetching the image data or the display output.
And now, in the technology disclosed in the above-mentioned Japanese Patent Application Laid-open publication No. 8-22268, a delay time of the display timing signal (latch signal) for each driver circuit is made by utilizing delay of the output circuit provided in each driver circuit. This delay time varies for each product driver circuit depending on manufacturing conditions, and its control is not easy. In addition, even in the same product driver circuits, this delay time varies depending on a temperature of the environment and a source voltage, and its control is also not easy.
On the other hand, to control the EMI of the display device, it is necessary to control in a manner that a resonance frequency as an EMI antenna, and an operation frequency are not equal. Here, Multiple EMI antennas are generally provided for each display device, and the operation frequency which periodically increases a source current of the driver circuit flowing through the power-supply lines of the device. However, by the technology disclosed in Japanese Patent Application Laid-open publication No. 8-22268, its control is not easy because of the above-described reason. As a result, there is a disadvantage in that the EMI of the display device cannot be prevented from occurring depending on the combination of the device and the driver circuit mounted thereon or the usage environment.